Method to reduce the depth of a buried contact trench by using a thin split polysilicon thickness
US6001681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.