Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology
US6001690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
Abstract
A method is provided for forming nitride spacers for flash EEPROM devices. A silicon nitride layer is formed over the floating gate in a memory cell. Unlike in conventional methods where the nitride layer is usually subjected to anisotropic etching, it is disclosed in this invention that when partial isotropic/anisotropic etching of a particular recipe is performed, the resulting nitride spacers are better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths during subsequent implantations. In a second embodiment, the partial isotropic/anisotropic etching is followed by full anisotropic etching of another recipe with even better defined parameters for the flash EEPROMS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.