Method to form ultra-short channel MOSFET with a gate-side airgap structure

US6001695A · kind A · utility

Assignee

• Texas Instruments-Acer Incorporated · TW

Inventor

• Shye-Lin Wu · 東區, TW

Key dates

• Filing date: Mar 2, 1998
• Grant date: Dec 14, 1999
• Expiry date: Mar 2, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

First, a field oxide region, a pad oxide layer and a first nitride layer are formed on a silicon substrate, respectively. Then, a portion of the first nitride layer is removed. A first oxide layer and a nitride spacer are formed on the substrate, respectively. Portions of the first oxide layer and the pad oxide layer are removed to form a first region of the first oxide layer and a second region of the first oxide layer. Then, an ion implantation is performed to form a punch-through stopping region. Next, a second oxide layer and an amorphous-Si layer are formed on the substrate, respectively. Portions of the a-Si layer are etched back. Next, the first nitride layer and the nitride spacer are removed. An ion implantation is performed to form a source, a drain and a doped region at the bottom of the second region of the first oxide layer. Then, a Rapid Thermal Process is used to drive dopant diffusion to form an extended source/drain junction. A third oxide layer is deposited on the substrate, wherein an air-gap is formed between the first region of the first oxide layer and a-Si layer. Finally, portions of the third oxide layer and the pad oxide layer are etched back to form an oxi…