Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set
US6001717A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making low-resistance contacts between polycide layers for local interconnections is achieved. The method is particularly useful for making low contact resistance R.sub.c between the tungsten polycide layers for local interconnections on the periphery of the DRAM chip. A first polycide layer is patterned to form FET gate electrodes and portions of local interconnections. An interlevel dielectric layer is deposited over the patterned first polycide layer. Contact openings are etched in the dielectric layer to the surface of the substrate and to the first polycide layer. A second polycide layer is deposited and patterned to form bit lines in the memory cell areas of the DRAM, while concurrently forming local interconnections in the peripheral device areas. A high-temperature rapid thermal anneal (RTA) is carried out to substantially reduce the contact resistance in the contact openings over the first polycide layer in the peripheral areas. This RTA eliminates the need for overetching the first silicide in the contact holes, as commonly practiced in the prior art. The RTA of this invention with a traditional N.sub.2 anneal prior to the second polycide deposition results i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.