Wan-Yih Lien
15Patents
10h-index
22Co-inventors
64Inventor score
Filing activity: May 7, 1998 → Apr 2, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6037216A | Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process | Electricity | 65 | Expired |
| US6022776A | Method of using silicon oxynitride to improve fabricating of DRAM contacts and landing pads | Electricity | 45 | Expired |
| US6673683B1 | Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions | Electricity | 33 | Expired |
| US6080664A | Method for fabricating a high aspect ratio stacked contact hole | Electricity | 28 | Expired |
| US6124165A | Method for making openings in a passivation layer over polycide fuses using a single mask while forming reliable tungsten via plugs on DRAMs | Electricity | 23 | Expired |
| US6338993B1 | Method to fabricate embedded DRAM with salicide logic cell structure | Electricity | 16 | Expired |
| US6001717A | Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set | Electricity | 15 | Expired |
| US6103623A | Method for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedure | Electricity | 14 | Expired |
| US6136646A | Method for manufacturing DRAM capacitor | Electricity | 10 | Expired |
| US6211091A | Self-aligned eetching process | Electricity | 10 | Expired |
| US6074952A | Method for forming multi-level contacts | Electricity | 7 | Expired |
| US6876027B2 | Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence | Electricity | 5 | Expired |
| US6096579A | Method for controlling the thickness of a passivation layer on a semiconductor device | Electricity | 5 | Expired |
| US6303955A | Dynamic random access memory with slanted active regions | Emerging Cross-Sectional Technologies | 2 | Expired |
| US7071478B2 | System and method for passing particles on selected areas on a wafer | Electricity | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.