SiC semiconductor device comprising a pn junction with a voltage absorbing edge
US6002159A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1996 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Jul 16, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor component including a silicon carbide substrate. A pn junction includes doped layers of the substrate. The pn junction includes at a surface of the substrate a low doped first conductivity type layer and at a portion of the surface of the substrate a highly doped second conductivity type layer. An edge termination region of the pn junction laterally surrounds the pn junction provided at an edge of at least one of the layers of the pn junction. The edge termination region includes zones of the second conductivity type located at an edge of the highly doped second conductivity type layer. A charge content of the zones decreases toward an edge of the edge termination region in accordance with at least one characteristic selected from the group consisting of a stepwise or continuously decreasing total charge towards an outer border of the edge termination region and a decreasing effective sheet charge density toward an outer border of the edge termination region. An outermost zone of the edge termination region is completely depleted at full design voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.