Unit cell layout and transfer gate design for high density DRAMs

US6004844A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Johann Alsmeier · San Jose, US
• Martin Gall · Kalamazoo, US

Key dates

• Filing date: Jul 15, 1996
• Grant date: Dec 21, 1999
• Expiry date: Jul 15, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/373

Abstract

A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.