Method to increase DRAM capacitor via rough surface storage node plate
US6004857A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A process for forming a crown shaped, storage node structure, for a DRAM capacitor structure, with a roughened top surface topology, needed for increased surface area, has been developed. The process features the use of a tungsten silicide layer, used as a component of the storage node structure, with the tungsten silicide layer, subjected to subsequent procedures, providing the roughened top surface topology for the storage node structure. The tungsten silicide layer, after deposition, is subjected to an oxidation procedure, followed by removal of the formed oxide layer, from a bottom portion of unoxidized tungsten silicide layer, resulting in the desired, roughened top surface topology, of the bottom portion of unoxidized tungsten silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.