Method for silicide stringer removal in the fabrication of semiconductor integrated circuits
US6004878A · kind A · utility
30Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Feb 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be etched selectively to the material selected as the isolation dielectric. A layer of silicide forming metal is deposited overlying the MOS transistor and heated, wherein silicide regions are formed where the metal makes contact with silicon, for example, in the gate electrode and source/drain regions. At least a portion of the sidewall spacers are etched-away and silicide stringers, if formed on the spacers, are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.