PLL using pulse width detection for frequency and phase error correction
US6005425A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Feb 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL in uses pulse width detection to provide frequency/phase error correction for a DCO. A pulse width detector is implemented using fine and coarse detection circuits which provide selectable fine and coarse detection granularity. Both the fine and coarse detection circuits use a number of individual detector elements coupled in sequence--a phase error pulse propagates through the detector elements which quantize pulse width detection. Each detector element includes a pulse width detect latch that latches an phase error pulse width indication for the current cycle and the previous cycle. A comparator determines in each cycle whether the phase error pulse width has changed--a phase correction signal is generated if either (a) the fine detection circuit detects that the phase error pulse width is increasing, or (b) the course detection circuit detects that the phase error is not decreasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.