VIA-Cyrix, Inc.
31Patents
1Active
31Granted
33Portfolio score
Filing activity: Aug 19, 1993 → Aug 13, 2003 · 1 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6351789B1 | Built-in self-test circuit and method for validating an associative data array | Physics | 90 | Expired |
| US6138230A | Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline | Physics | 65 | Expired |
| US6219773A | System and method of retiring misaligned write operands from a write buffer | Physics | 62 | Expired |
| US6205560A | Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG | Physics | 44 | Expired |
| US6073231A | Pipelined processor with microcontrol of register translation hardware | Physics | 41 | Expired |
| US6351797B1 | Translation look-aside buffer for storing region configuration bits and method of operation | Physics | 33 | Expired |
| US5996071A | Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address | Physics | 29 | Expired |
| US6239627A | Clock multiplier using nonoverlapping clock pulses for waveform generation | Electricity | 29 | Expired |
| US6005425A | PLL using pulse width detection for frequency and phase error correction | Electricity | 22 | Expired |
| US6065091A | Translation look-aside buffer slice circuit and method of operation | Physics | 20 | Expired |
| US6115730A | Reloadable floating point unit | Physics | 14 | Expired |
| US6301647A | Real mode translation look-aside buffer and method of operation | Physics | 11 | Expired |
| US6032241A | Fast RAM for use in an address translation circuit and method of operation | Physics | 11 | Expired |
| US6381622B1 | System and method of expediting bit scan instructions | Physics | 10 | Expired |
| US7143243B2 | Tag array access reduction in a cache memory | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7013383B2 | Apparatus and method for managing a processor pipeline in response to exceptions | Physics | 9 | Expired |
| US7177981B2 | Method and system for cache power reduction | Emerging Cross-Sectional Technologies | 8 | Expired |
| US6412063B1 | Multiple-operand instruction in a two operand pipeline and processor employing the same | Physics | 7 | Expired |
| US6009533A | Speculative bus cycle acknowledge for 1/2X core/bus clocking | Physics | 7 | Expired |
| US6442635B1 | Processor architecture for virtualizing selective external bus transactions | Physics | 7 | Expired |
| US7024544B2 | Apparatus and method for accessing registers in a processor | Physics | 6 | Expired |
| US6209083A | Processor having selectable exception handling modes | Physics | 6 | Expired |
| US6844767B2 | Hierarchical clock gating circuit and method | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6983359B2 | Processor and method for pre-fetching out-of-order instructions | Physics | 5 | Expired |
| USRE39385E1 | Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier | General | 5 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.