Vertical connector based packaging solution for integrated circuits
US6005776A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Jan 5, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An assembly featuring a substrate and a plurality of components. The plurality of components are packaged to be connected in a vertical orientation to the substrate. These components include (i) a vertical chip-scale package (CSP), (ii) an integrated circuit die and (iii) an interconnect. Including a plurality of connection leads, the vertical CSP contains the die which is generally situated along a vertical plane. The interconnect, capable of transferring information between the plurality of connection leads and the integrated circuit die, includes a first segment generally perpendicular to the vertical plane and connected to at least one connection lead. The interconnect further includes a second segment generally in parallel to the vertical plane and connected to the integrated circuit die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.