Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations
US6005810A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Aug 10, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Aug 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and the counters are reset. The lifetime of the resulting flash memory system is improved because of decreased erase and program stresses in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.