Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance
US6008084A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/711
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a DRAM chip, featuring low resistance bit line structures, in a peripheral region, and a cell array containing bit line structures exhibiting low bit line to bit line coupling capacitance, has been developed. The process features creating a first damascene opening, in insulator layers in the peripheral region of the DRAM cell, in which the top portion of the first damascene opening is comprised of a deep trench shape, allowing for low resistance bit line structures, when filled with a conductive material. The process also features the creation of second damascene openings, in an insulator layer in the cell array region of the DRAM chip, with the top portion of the second damascene openings exhibiting a shallow trench shape, again allowing bit line structures to be created after filling again with a conductive layer, but with low bit line to bit line coupling capacitance, achieved as a result of the thin metal fill, in the shallow trench opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.