Design and a novel process for formation of DRAM bit line and capacitor node contacts
US6008085A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.