Micro-trench oxidation by using rough oxide mask for field isolation
US6008106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Aug 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7621
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.