Electrical fuses with tight pitches and method of fabrication in semiconductors
US6008523A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link. The common connector terminal cross sectional area is desirably about 2 or more times that of the individual fuse links to enable electrical fusing at voltages of about 10 volts or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.