Axel Brintzinger
41Patents
15h-index
49Co-inventors
73Inventor score
Filing activity: Mar 9, 1998 → Oct 14, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6720212B2 | Method of eliminating back-end rerouting in ball grid array packaging | Electricity | 69 | Expired |
| US6433404B1 | Electrical fuses for semiconductor devices | Electricity | 60 | Expired |
| US6495918B1 | Chip crack stop design for semiconductor chips | Electricity | 55 | Expired |
| US6251710A | Method of making a dual damascene anti-fuse with via before wire | Electricity | 52 | Expired |
| US6008523A | Electrical fuses with tight pitches and method of fabrication in semiconductors | Electricity | 35 | Expired |
| US6252292A | Vertical electrical cavity-fuse | Electricity | 27 | Expired |
| US6242789A | Vertical fuse and method of fabrication | Electricity | 24 | Expired |
| US6323535A | Electrical fuses employing reverse biasing to enhance programming | Electricity | 24 | Expired |
| US6486526B1 | Crack stop between neighboring fuses for protection from fuse blow damage | Electricity | 22 | Expired |
| US6274440A | Manufacturing of cavity fuses on gate conductor level | Electricity | 20 | Expired |
| US6218279A | Vertical fuse and method of fabrication | Electricity | 20 | Expired |
| US6465282B1 | Method of forming a self-aligned antifuse link | Electricity | 20 | Expired |
| US6288436A | Mixed fuse technologies | Electricity | 18 | Expired |
| US6261937A | Method for forming a semiconductor fuse | Electricity | 18 | Expired |
| US7087975B2 | Area efficient stacking of antifuses in semiconductor device | Electricity | 16 | Expired |
| US6882027B2 | Methods and apparatus for providing an antifuse function | Electricity | 15 | Expired |
| US6943101B2 | Manufacturing of a corrosion protected interconnect on a substrate | Electricity | 13 | Expired |
| US6638870B2 | Forming a structure on a wafer | Electricity | 13 | Expired |
| US6458631B1 | Method for fabricating an integrated circuit, in particular an antifuse | Electricity | 9 | Expired |
| US6060398A | Guard cell for etching | Electricity | 9 | Expired |
| US6888215B2 | Dual damascene anti-fuse with via before wire | Electricity | 7 | Expired |
| US6866943B2 | Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6566238B2 | Metal wire fuse structure with cavity | Electricity | 6 | Expired |
| US6495901B2 | Multi-level fuse structure | Electricity | 5 | Expired |
| US6919264B2 | Method for the solder-stop structuring of elevations on wafers | Electricity | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.