Contactless array configuration for semiconductor memories
US6009013A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.