Compressed input/output test mode
US6009026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Jul 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.