Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6009261A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture. Target routines (corresponding to the incompatible instruction instances in an incompatible program being emulated) are accessed, patched where necessary, and executed by a target processor to enable the target processor to precisely obtain the execution results of the emulated incompatible program. Before preprocessing, each…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.