Method for making a ferroelectric device having a tantalum nitride barrier layer

US6010927A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Robert E. Jones · Austin, US
• Peir Chu · Pflugerville, US
• Peter Zurcher · Dripping Springs, US
• Ajay Jain · Austin, US

Key dates

• Filing date: Oct 28, 1997
• Grant date: Jan 4, 2000
• Expiry date: Oct 28, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.