Circuit and method for the erasure of a non-volatile and electrically erasable memory
US6011724A · kind A · utility
6Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the erasure of a non-volatile and electrically erasable memory in which the amplitude of the pulses that are sent to erase the memory varies as a function of the number of pulses previously sent. A circuit for the generation of erasure pulses of variable amplitude for a non-volatile and electrically erasable memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.