Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
US6012118A · kind A · utility
29Cited by
7References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.