Peter D. MacWilliams
61Patents
26h-index
61Co-inventors
91Inventor score
Filing activity: Jan 26, 1988 → Aug 17, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6587912B2 | Method and apparatus for implementing multiple memory buses on a memory module | Physics | 322 | Expired |
| US6477614B1 | Method for implementing multiple memory buses on a memory module | Physics | 244 | Expired |
| US5355467A | Second level cache controller unit and system | Physics | 177 | Expired |
| US6075730A | High performance cost optimized memory with delayed memory writes | Physics | 151 | Expired |
| US5905876A | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system | Physics | 117 | Expired |
| US5228134A | Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus | Physics | 96 | Expired |
| US5822767A | Method and apparartus for sharing a signal line between agents | Physics | 84 | Expired |
| US5293603A | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path | Physics | 72 | Expired |
| US4785396A | Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit | Electricity | 69 | Expired |
| US5796977A | Highly pipelined bus architecture | Physics | 69 | Expired |
| US6112016A | Method and apparatus for sharing a signal line between agents | Physics | 69 | Expired |
| US6202125A | Processor-cache protocol using simple commands to implement a range of cache configurations | Physics | 60 | Expired |
| US5615343A | Method and apparatus for performing deferred transactions | Physics | 51 | Expired |
| US6226757A | Apparatus and method for bus timing compensation | Physics | 50 | Expired |
| US5906001A | Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines | Physics | 44 | Expired |
| US5572703A | Method and apparatus for snoop stretching using signals that convey snoop results | Physics | 42 | Expired |
| US5625779A | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | Physics | 41 | Expired |
| US6633947B1 | Memory expansion channel for propagation of control and request packets | Physics | 40 | Expired |
| US5651137A | Scalable cache attributes for an input/output bus | Physics | 37 | Expired |
| US5919254A | Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system | Physics | 32 | Expired |
| US5903916A | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation | Physics | 30 | Expired |
| US6012118A | Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus | Physics | 29 | Expired |
| USRE38388E1 | Method and apparatus for performing deferred transactions | General | 29 | Expired |
| US6247136A | Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment | Physics | 27 | Expired |
| US5513331A | Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset | Physics | 27 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.