Multiprocessor computing apparatus with optional coherency directory
US6012127A · kind A · utility
22Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.