Method of manufacturing a split-gate flash memory cell
US6013552A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 1998 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Jun 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
In a method of manufacturing a split-gate flash memory cell including source and drain diffusion regions (6 and 9), a floating gate insulation film (2), a floating gate electrode (3), a control gate insulation film (4), and a control gate electrode (10), the method includes the steps of: successively forming the floating gate insulation film (2) and the floating gate electrode (3) on a selected area of a semiconductor substrate (1); forming the control gate insulation film (4) on the floating gate electrode (3) and on a remaining area of the semiconductor substrate (1), the control gate insulation film (4) having a side wall part brought into contact with a side wall of the floating gate electrode (3); carrying out ion-implantation of a first dopant to form the source diffusion region (6) on a first part of the remaining area of the semiconductor substrate (1); forming a sidewall electrode (8) brought into contact with the sidewall part of the control gate insulation film (4); carrying out ion-implantation of a second dopant to form, on a second part of the remaining area of the semiconductor substrate (1), the drain diffusion region (9) self-aligned with respect to the sidewall el…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.