Amplifier MOS biasing circuit for a avoiding latch-up
US6014053A · kind A · utility
9Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 12, 1997 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | May 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45076
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.