Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US6014509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed. Logic cells are directly connected to neighboring nearest cells, including diagonally and orthogonally adjacent cells, and are also connected to local bus lines. Such direct cell-to-cell connections allow both directions of signal propagation. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, I/O pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.