Production method of a vertical type MOSFET
US6015737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 1995 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Aug 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.