Method of manufacturing a shallow trench isolation alignment mark
US6015744A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a shallow trench isolation alignment mark comprises the steps of first providing a silicon wafer whose surface has an alignment mark formed thereon. Next, a silicon nitride layer is formed over the silicon wafer, and then shallow trenches are formed. At least one of the shallow trenches is positioned at a distance of about 2000 .ANG. to 10000 .ANG. from the edge of the alignment mark. Thereafter, an oxide layer is formed over the silicon nitride layer, and then a chemical-mechanical polishing operation is conducted to remove a portion of the oxide layer and silicon nitride layer above the alignment mark. Altogether, a layer of silicon nitride having a thickness of about 600 .ANG. is removed from the top of the alignment mark. Finally, the silicon nitride layer is also removed. By forming a shallow trench at a distance of between 2000 .ANG. to 10000 .ANG. from the edge of an alignment mark, accurate overlaying of mask can be achieved without the need for performing additional oxide clearout operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.