United Silicon Incorporated
64Patents
0Active
64Granted
37Portfolio score
Filing activity: Apr 8, 1998 → Nov 23, 1999
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6114238A | Self-aligned metal nitride for copper passivation | Electricity | 71 | Expired |
| US6159845A | Method for manufacturing dielectric layer | Electricity | 70 | Expired |
| US6020606A | Structure of a memory cell | Electricity | 34 | Expired |
| US6069037A | Method of manufacturing embedded DRAM | Electricity | 31 | Expired |
| US5994197A | Method for manufacturing dynamic random access memory capable of increasing the storage capacity of the capacitor | Electricity | 27 | Expired |
| US6180493A | Method for forming shallow trench isolation region | Electricity | 25 | Expired |
| US6001716A | Fabricating method of a metal gate | Electricity | 24 | Expired |
| US6191029A | Damascene process | Electricity | 21 | Expired |
| US6165279A | Method for cleaning a semiconductor wafer | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6090698A | Fabrication method for an insulation structure having a low dielectric constant | Electricity | 18 | Expired |
| US6058059A | Sense/output circuit for a semiconductor memory device | Physics | 17 | Expired |
| US6194279A | Fabrication method for gate spacer | Electricity | 17 | Expired |
| US6153528A | Method of fabricating a dual damascene structure | Electricity | 15 | Expired |
| US6169017A | Method to increase contact area | Electricity | 15 | Expired |
| US5963819A | Method of fabricating shallow trench isolation | Electricity | 14 | Expired |
| US6156608A | Method of manufacturing cylindrical shaped capacitor | Electricity | 14 | Expired |
| US6069032A | Salicide process | Electricity | 13 | Expired |
| US6093600A | Method of fabricating a dynamic random-access memory device | Electricity | 12 | Expired |
| US6262580A | Method and testing system for measuring contact resistance for pin of integrated circuit | Physics | 12 | Expired |
| US6015744A | Method of manufacturing a shallow trench isolation alignment mark | Electricity | 11 | Expired |
| US6180477A | Method of fabricating field effect transistor with silicide sidewall spacers | Electricity | 11 | Expired |
| US6127228A | Method of forming buried bit line | Electricity | 11 | Expired |
| US6111293A | Silicon-on-insulator MOS structure | Electricity | 10 | Expired |
| US6010943A | Method of fabricating a cylindrical capacitor | Electricity | 10 | Expired |
| US6150237A | Method of fabricating STI | Electricity | 9 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.