Capacitor with oxide/nitride/oxide composite dielectric suitable for embedded nonvolatile memory in analog applications
US6015984A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Sep 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02263
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process for making embedded memory cells is disclosed which is based on a bifurcated two-polysilicon structure. The embedded memory cell contains a memory cell portion and an embedded capacitor portion. The memory cell portion contains a floating gate, a control gate and an oxide/nitride/oxide (ONO) layer sandwiched therebetween, and the embedded capacitor portion similarly contains a top electrode, a bottom electrode, and an oxide/nitride/oxide layer also sandwiched therebetween. The floating gate and the bottom electrode of the embedded capacitor portion are simultaneously made from the same poly1 layer. However, unlike the prior art devices, the poly1 layer is bifurcated via simple photolithographic sequences such that the bottom electrode of the embedded capacitor portion has a high degree of doping than the floating gate. As a result, the bifurcated two-polysilicon structure provides the same level of performance, with regard to both the memory cell portion and the capacitor portin, as the conventional three-polysilicon structure, and no comprise is necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.