Thin liner layer providing reduced via resistance
US6016012A · kind A · utility
36Cited by
16References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1996 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Nov 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.