High-precision analog reading circuit for flash analog memory arrays using negative feedback
US6016272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog reading circuit having a current mirror circuit forcing two identical currents into a cell to be read and into a reference cell. An operational amplifier has an inverting input connected to the drain terminal of the cell to be read, a non-inverting input connected to the drain terminal of the reference cell, and an output connected to the gate terminal of the reference cell. The reference cell therefore forms part of a negative feedback loop which maintains the overdrive voltages of the cell to be read and the reference cell constant, irrespective of temperature variations. The reading circuit is also of high precision and has a high reading speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.