Method for handling data cache misses using help instructions
US6016532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction. The bypass help instruction causes the datum requested by the miss instruction to be forwarded to the destination of the miss instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.