Output data compression scheme for use in testing IC memories
US6016561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of oper…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.