Method for forming a polysilicon/amorphous silicon composite gate electrode
US6017819A · kind A · utility
13Cited by
15References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.