Semiconductor flip chip package
US6018196A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1383
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.