Line decoder for memory devices
US6018255A · kind A · utility
3Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 1997 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | May 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.