Double buffering operations between the memory bus and the expansion bus of a computer system
US6018620A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1996 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Mar 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.