Identifying an optimizable logic region in a logic network
US6018621A · kind A · utility
7Cited by
8References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.