Single layer integrated metal process for enhancement mode field-effect transistor
US6020226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28581
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an enhancement mode periodic table group III-IV metal semiconductor metal field-effect transistor is described. The disclosed fabrication arrangement uses single metallization for ohmic and Schottky barrier contacts, employs initially undoped semiconductor materials--materials selectively doped in a disclosed processing step, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence along with permanent surface passivation. The invention uses a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor capable of microwave frequency use, of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and state of the art electrical performance. Fabricated device characteristics are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.