CMOS device structure with reduced short channel effect and memory capacitor
US6020228A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.