Method to form capacitance node contacts with improved isolation in a DRAM process
US6020236A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.