Effective silicide blocking
US6020242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described. The process includes forming a gate electrode above the integrated circuit substrate, forming a first dielectric layer over the gate electrode and the substrate surface, forming a second dielectric layer above the first dielectric layer, etching anisotropically the second dielectric layer to form a second spacer portion adjacent to the first dielectric layer; masking the substrate surface of the first device to protect the first dielectric layer above the first device from being removed such that the substrate surface at the second device where the metal silicide is to be formed is exposed, etching the first dielectric layer to form a first spacer portion disposed between the gate electrode of the second device and the second spacer portion, the first spacer portion extends underneath the second spacer portion such that the first spacer portion is disposed between the second spacer portion and a portion of the substrate disposed beneath the second spacer portion, exposi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.