Printed circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereof
US6020561A · kind A · utility
113Cited by
10References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.