Semiconductor memory device having contact holes of differing structure

US6020643A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Yoshiaki Fukuzumi · Yokkaichi, JP
• Yusuke Kohyama · Yokosuka, JP

Key dates

• Filing date: Jul 14, 1998
• Grant date: Feb 1, 2000
• Expiry date: Jul 14, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

A semiconductor memory device comprises a semiconductor substrate, a first conducting layer formed above the main surface of the semiconductor substrate, a second conducting layer formed above the first conducting layer through a first insulating layer and connected to the first conducting layer through a first via-conductor formed in a first contact hole formed in the first insulating layer, and a third conducting layer formed beneath the second conducting layer through a second insulating layer and connected to the second conducting layer through a second via-conductor formed in a second contact hole formed in the second insulating layer, in which an angle formed by a tangent to an inner wall of the first contact hole and a normal to the first conducting layer at a portion of the first conducting layer at which the first contact hole is in contact with the first conducting layer, is larger than an angle formed by a tangent to an inner wall of the second contact hole and a normal to the third conducting layer at a portion of the third conducting layer at which the second contact hole is in contact with the third conducting layer. By virtue of this structure, it is possible to avoi…