Partially reconfigurable programmable logic device
US6020758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1996 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Mar 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17756
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.