NVRAM utilizing high voltage TFT device and method for making the same

US6022770A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Terence B. Hook · Jericho, US
• James S. Nakos · Saint Johnsbury Center, US
• Richard Q. Williams · South Burlington, US

Key dates

• Filing date: Mar 24, 1998
• Grant date: Feb 8, 2000
• Expiry date: Mar 24, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and increasing potential integration density by using thin film transistors for high voltage switching and isolating the thin film transistors from the substrate by forming the thin film transistors on isolation structures extending between or over elements formed at a surface of a substrate or semiconductor layer. Geometry and doping levels of the thin film transistors is thus made independent of geometry and doping levels of the non-volatile semiconductor memory cells and other field effect transistors operating at lower logic-level voltages. In particular, the thickness of a doped semiconductor layer in which an impurity well may be formed can be determined in a manner to optimize performance of transistors operating at logic level voltages rather than the breakdown voltage which must be withstood by transistors used for controlling write and erase operations of the non-volatile memory cells.